Radio frequency (RF) receivers, such as receivers used in radar systems, process analog RF input signals using one or more analog to digital converters (ADCs) that sample the analog input and convert the analog input signal into a digital signal for further processing. It is desirable for an RF receiver to have a high dynamic range corresponding to a band of frequencies within the receiver's band of operation. Additionally, it is desirable that the receiver have wide bandwidth, that is, the ability to receive and process signals transmitted across a wide range of frequencies. In receiver design, the desire for increased dynamic range and wideband operation creates tradeoffs where the designer must choose from design options which increase one of dynamic range and wide bandwidth at the expense of the other.
One architecture which has been developed to increase narrowband dynamic range is the provision of dual ADCs. In one example of a dual ADC architecture, the outputs of the dual ADCs outputs are summed to increase the signal to noise ratio (SNR) for the operating band of the receiver. When using summed ADCs, two ADCs sample the analog input signal. The input signal is mixed down using a common local oscillator (LO) associated with both ADCs, which samples the input signal produced by the common LO. The output signals of the ADCs are synchronized by virtue of the common LO and therefore can be directly summed to provide up to an increase in SNR of about 3 dB.
A second architecture uses interleaved ADCs. Interleaved ADCs use interleaved clock signals which are used to increase the effective sampling rate of the receiver using multiple ADCs with each ADC receiving a delayed clock signal relative to other ADCs. For example, in a receiver where the clock signal is delayed and interleaved with the original clock signal, the effective sampling rate may be increased by a factor of two for each clock signal.
IQ processing involving a Quadrature Demodulation may be used, however IQ processing raises concerns regarding images, LO and direct current (DC) leakage.
Stacked ADCs use a number of ADCs operating at different receiver gains to compensate for increased power levels of return signals reflected off of objects located nearer to the receiver relative to other objects. Gain levels may vary within the receiver time window, creating a form of sensitivity time control (STC).
Complex ADCs (CADCs) have been developed, which operate like an interleaved ADC where complex weighting is used during the summing of the ADC outputs. However, interleaving spurs and calibration issues create problems which must be addressed.
In addition to architectures using dual or multiple ADCs, parallel receivers have also been developed where separate parallel receivers each process a portion of the receiver bandwidth. The outputs of each parallel receiver are combined to define the bandwidth of the overall receiver. However, because each ADC is processing a different band of frequencies, the ability to increase the dynamic range of a parallel receiver is limited.
Methods and architectures which provide improved dynamic range and wideband operation are desired.